/*
*	Here is where General Registers are.
*	Total number is 32 from 0 to 31.
*	2011.4.6(done)
*/

module Reg_Files(
	clk,	//clock
	A1,		//rs
	A2,		//rt
	A3,		//rd
	WD3,	//contents ready to write in R[rd]
	WE3,	//writable
	RD1,	//R[rs]
	RD2		//R[rt]
);
	input[4:0] A1,A2,A3;
	input[31:0] WD3;
	input clk,WE3;
	output[31:0] RD1,RD2;
	reg[31:0] data[0:31],RD1,RD2;
	integer i;
	
	//$0 is the zero register only containing zero
	initial data[0] <= 0;
	integer temp1,temp2;
	
	//initial
	initial begin
		for(i = 0 ; i < 32 ; i = i+1)
			data[i] = 0;
		RD1 = 0;
		RD2 = 0;
	end
	
	//Up Edge for Write
	always @(posedge clk) begin
		if(WE3) begin
			temp1 = A3;
			if(temp1 != 0) data[temp1] = WD3;
		end
	end
	
	//Down Edge for Read
	always @(negedge clk) begin
		temp1 = A1;
		RD1 = data[temp1];
		temp2 = A2;
		RD2 = data[temp2];
		
		/* for test
		for(i = 0; i < 4 ; i = i+1)
			$display("time = %0d,reg[%0d] = %0d",$time,i,data[i]);
		$display("time = %0d,reg[%0d] = %0d, reg[%0d] = %0d",$time,temp1,data[temp1],temp2,data[temp2]);
		//*/
	end
endmodule
